The present invention relates generally to data processing system and, more particularly, to a data processing system capable of correcting the higher order address when a carry or borrow signal is generated in address computation.
FIG. 6 shows the central processing unit (CPU) of a conventional microcomputer. It is assumed that the address width and data bus width are 24 and 16 bits, respectively. The CPU includes a program counter (PC) 1, a program bank register (PBR) 2, a data bank register (DBR) 3, address latches (L1 and L2) 5 and 6, address adders (INC1 and INC2) 7 and 8, an arithmetic and logic unit (ALU) 21, and buses for connecting these devices. The PC 1, and the PBR 2 and DBR 3 are a 16-bit register and 8-bit registers, respectively. The PBR 2 holds the most significant 8 bits (AD.sub.16 -AD.sub.23) of an address in the program area while the DBR 3 holds values in the most significant 8 bits of an address in the data area, respectively. Consequently, the program fetch is carried out from the address at which the most significant 8 bits AD.sub.16 -AD.sub.23 are designated by the contents of the program bank register and AD.sub.0 -AD.sub.15 are designated by the contents of the program counter. On the other hand, the data fetch is carried out from the address at which AD.sub.16 -AD.sub.23 and AD.sub.0 -AD.sub.15 are designated by the contents of the DBR 3 and the values determined by the operation of the CPU in execution of the instruction, respectively.
The CPU further includes various 16-bit registers 10-18; namely, a temporary register (TP1) 10 for temporary storing the results of computation in the ALU 21, accumulators (A and B) 11 and 12, and index registers (X and Y) 13 and 14, a stack pointer (S) 15, a direct page register (D) 16, a processor status register (PS) 17, and a temporary register (TP2) 18 for temporary storing data fetched into the CPU from the data bus, and internal bus latches 19 and 20. Symbols o and o represent gates responsive to a control signal from the control section to open when the reference clock is a logic level low "L" and a logic level high "H", respectively.
The operation of the CPU will be described by way of the execution of an instruction Load Accumulator A (LDA) in an absolute X addressing mode. This instruction is composed of one byte of operation code and two bytes of operand. A first address part identified by the sum of the contents of the X register and the operand are used as a low part of an address to be combined with a second address part stored in DBR 3 to provide an entire address. This entire address is used to access data which is loaded into accumulator A.
The timing chart for execution of this instruction is shown in FIG. 7. In cycles 30 and 31, the operation code and the operand are fetched, and the operation code is decoded. At the same time, the previous instruction is executed in these cycles. Consequently, the LDA instruction is executed from the next cycle 32, in which the 2-byte operand (hhll) fetched in the TP2 in the previous cycle and the contents of the X register are added in the ALU 21 and the sum is stored in the TP1. In the next cycle 33, the values of this TP1 and the DBR are output at AD.sub.0 -AD.sub.15 and AD.sub.16 -AD.sub.23, respectively, and the contents of this address is fetched in the TP2. In the cycle 34, the fetched value is transferred to the TP1 to check the flag. In the cycle 35, it is stored in the accumulator A. Thus, the execution of the LDA instruction in the absolute X addressing mode is completed in four cycles.
However, there is a problem when a carry signal is generated upon addition of the contents of the X register and the operand hhll in the cycle 32. The 16-bit addition in the ALU 21 generates a carry signal in the second half of the cycle 32 so that there is not sufficient time to input it to the address adder 8 of FIG. 6 to increment by one digit the value of the DBR 3 in the same cycle.
One solution is to ignore all carry signals. However, this results in loss of the continuity in the memory area, which is disadvantageous for programming purposes. Another solution is to provide after the cycle 32 another cycle for computing the value of the DBR 3 and a carry signal in the ALU 21. This makes the execution time one cycle longer.